Junji Ogawa

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A split capacitor DAC calibration method is proposed that a bridge capacitor larger than conventional design allows a tunable capacitor to compensate for mismatch. To guarantee proper calibration, a comparator with digital timing control offset cancellation is proposed. An 8-bit successive approximation ADC with 4b+4b split capacitor DAC calibration has(More)
A high bandwidth and a robust performance are demanded in the consumer market applications. An ADC-based transceiver satisfies these demands and enables power/area scaling with process [1,2]. We developed and tested a spread-spectrum-clocking (SSC) compliant 5-Gb/s transceiver in 65-nm CMOS. The receiver uses an ADC-based front-end that samples the incoming(More)
—This paper presents an ADC-based CDR that blindly samples the received signal at twice the data rate and uses these samples to directly estimate the locations of zero crossings for the purpose of clock and data recovery. We successfully confirmed the operation of the proposed CDR architecture at 5 Gb/s. The receiver is implemented in 65 nm CMOS, occupies(More)
SUMMARY Seismic hazard analysis is performed for a representative zone in Peru, including the city of Cusco, the citadel of Machupicchu and the archeological complex of Choquequirao, constituting the area with important Inca heritage. This is considered to be the first step towards developing a rational approach to seismic risk analysis of the Inca's(More)
SUMMARY This paper describes an 18-GHz coupled VCO array for low jitter and low phase deviation clock distribution. To reduce the skew, jitter and power consumption associated with clock distribution, the clock is generated by a one-dimensional VCO array in which the oscillating nodes of adjacent VCOs are directly connected with wires. The effects of the(More)
We describe a 16-channel 2.5Gb/s high-speed transceiver that operates off a single supply voltage ranging from 0.8V to 1.3V. We fabricated the transceiver in a 90nm standard CMOS, using CMOS full-swing circuits except for a limited number of speed- and timing-critical circuits that were implemented in reduced-swing circuit topologies. The reduced-swing(More)