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A non-resistance readout scheme for high density multi-level PCRAM is described. Non-resistance read metric with drift resilient nature is enhanced to be suitable for high density memory array with large parasitic time constant. 1G PCM cells in 25nm technology are structured in the form of a single bank of a 16G cell chip with the hierarchical bit-line(More)
Recently, the 3D stacked memory, which is known as HBM (high bandwidth memory), using TSV process has been developed. The stacked memory structure provides increased bandwidth, low power consumption, as well as small form factor. There are many design challenges, such as multi-channel operation, microbump test and TSV connection scan. Various design(More)
A 10 Gb/s 4-level pulse amplitude modulation (PAM) transceiver was implemented using a 0.13 μm CMOS process. The implemented 4-PAM transmitter employs current mode logics (CMLs) for high-speed operations. The proposed 4-PAM transceiver achieves a channel efficiency of 2 bit/symbol with adaptive pre-emphasis. The pre-emphasis was designed to be(More)
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