Jun-Ha Lee

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For the first time, by employing low thermal budget processes of ALD SiO/sub 2/ and ALD SiN as gate spacer and silicide blocking layer, the short channel effects of CMOSFETs are significantly suppressed. Using the ALD SiO/sub 2/ and ALD SiN processes, we achieved excellent roll-off characteristics of threshold voltage in PMOS, which results in 10% increase(More)
This paper proposes a novel methodology of systematic global calibration of a process simulator and validates its accuracy and efficiency with application to memory and logic devices. With 175 SIMS profiles which cover the whole range of conditions of implant and diffusion processes in the fabrication lines, the dominant diffusion phenomenon in each process(More)
The current drive in an MOSFET is limited by the intrinsic channel resistance. All the other parasitic elements in a device structure play a significant role and degrade the device performance. These other resistances need to be less than 10%-20% of the channel resistance. To achieve the requirements, we should investigate the methodology of separation and(More)
In the case of the Hash memory, various kinds of transistors and the wide range of operation voltage are necessary to achieve the read/write operations. Therefore, the characteristics of transistors are measured in the silicon for the circuit design, and the test vehicle run must he processed. In this study, an efficient design flow is suggested using TCAD(More)
Problems of overlap errors and side-lobe printing by the design rule reduction in the lithography process using attenuated phase-shifting masks (attPSM) have been serious. Overlap errors and side-lobes can be simultaneously solved by the rule-based correction using scattering bars with the rules extracted from test patterns. Process parameters affecting the(More)
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