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An ultra-low-power 60 GHz low-noise amplifier (LNA) with a 12.5 dB peak gain and a 5.4 dB minimum NF is demonstrated in a 90 nm CMOS technology. The LNA is composed of four cascaded common-source stages with the gate-source transformer feedback applied to the input stage for simultaneous noise and input matching. Also, the drain-source transformer feedback(More)
Nuclear magnetic resonance imaging (MRI) is a powerful tool for non-invasive 3D imaging. Since the precession frequency of a nucleus is linearly proportional to the local magnetic field, a constant spatial gradient field generated by a gradient coil encodes the location of a signal. The imaging is achieved by spatially coding the precession(More)
A 70-GHz broadband amplifier is realized in a 0.13- mum CMOS technology. By using five cascaded common- source stages with the proposed asymmetric transformer peaking technique, the measured bandwidth and gain can reach 70.6 GHz and 10.3 dB under a power consumption (P<sub>DC</sub>) of 79.5 mW. Within the circuit bandwidth, the maximum input and output(More)
A fully integrated balanced amplifier was realized in a standard 0.18-mum CMOS technology. From the measured-parameters, a gain up to 21.5 dB was achieved at 45.4 GHz under a supply voltage of only 1 V and a total power consumption of 89 mW. An effective technique, i.e., pi-type parallel resonance, was proposed to enhance the device and circuit frequency(More)
A fully integrated frequency divider with an operation frequency up to 20 GHz is designed in 0.18m CMOS technology. The frequency divider includes two stages to divide the input signal by a factor of 4. A wide locking range from 18.8 to 23.2 GHz was obtained with a low phase noise of 134 8 dBc/Hz (1-MHz offset) at an output frequency of 4.7 GHz. The first(More)
The low-loss single semi-coaxial (S-SC) and differential semi-coaxial (D-SC) interconnects based on a standard 0.18-gm CMOS process are presented for the first time. Compared to the attenuation constant (a) reported for microstrip and CPW interconnects in CMOS process, the S-SC line shows the lowest loss of 0.90 dB/mm at 50 GHz. The D-SC line also presents(More)
Design, characterization, and modeling of differential semicoaxial interconnects based on a standard 0.18-mum CMOS process are presented for the first time. The differential semicoaxial line shows a low differential-mode attenuation constant of ~1.00 dB/mm at 50 GHz and a slow-wave factor above 3.1 over a wide frequency range. The characteristics of(More)