Jun-De Jin

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—A 3.1–10.6 GHz ultra-wideband (UWB) low noise amplifier (LNA) utilizing a current-reused technique and a simple high-pass input matching network is proposed. The implemented LNA presents a maximum power gain of 16 dB, and a good input matching of 50 in the required band. An excellent noise figure (NF) of 3.1–6 dB was obtained in the frequency range of(More)
—An ultra-low-power 60 GHz low-noise amplifier (LNA) with a 12.5 dB peak gain and a 5.4 dB minimum NF is demonstrated in a 90 nm CMOS technology. The LNA is composed of four cascaded common-source stages with the gate-source transformer feedback applied to the input stage for simultaneous noise and input matching. Also, the drain-source transformer feedback(More)
Nuclear magnetic resonance imaging (MRI) is a powerful tool for non-invasive 3D imaging. Since the precession frequency of a nucleus is linearly proportional to the local magnetic field, a constant spatial gradient field generated by a gradient coil encodes the location of a signal. The imaging is achieved by spatially coding the precession(More)
The low-loss single semi-coaxial (S-SC) and differential semi-coaxial (D-SC) interconnects based on a standard 0.18-gm CMOS process are presented for the first time. Compared to the attenuation constant (a) reported for microstrip and CPW interconnects in CMOS process, the S-SC line shows the lowest loss of 0.90 dB/mm at 50 GHz. The D-SC line also presents(More)
This paper presents a V-band low-noise amplifier with high RF performance and ESD robustness. An inductor-triggered silicon-controlled rectifier (SCR) assisted with both a PMOS and an inductor is proposed to enhance the ESD robustness and minimize the impact of the ESD protection block on the millimeter-wave LNA. The initial-on PMOS improves the turn-on(More)
— A 70-GHz broadband amplifier is realized in a 0.13-μm CMOS technology. By using five cascaded common-source stages with the proposed asymmetric transformer peaking technique, the measured bandwidth and gain can reach 70.6 GHz and 10.3 dB respectively under a power consumption (P DC) of 79.5 mW. With miniaturized transformer design, the core area of the(More)
—A fully integrated frequency divider with an operation frequency up to 20 GHz is designed in 0.18-m CMOS technology. The frequency divider includes two stages to divide the input signal by a factor of 4. A wide locking range from 18.8 to 23.2 GHz was obtained with a low phase noise of 134 8 dBc/Hz (1-MHz offset) at an output frequency of 4.7 GHz. The first(More)
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