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SUMMARY Future exascale systems are expected to adopt compute nodes that incorporate many accelerators. To shed some light on the upcoming software challenge, this paper investigates the particular topic of programming clusters that have multiple Xeon Phi coprocessors in each compute node. A new offload approach is considered for intra-node communication,(More)
The present study aimed to investigate the association between the content and distribution of fat in the pancreas and liver in patients with type 2 diabetes mellitus (T2DM). A total of 70 patients newly diagnosed with T2DM (T2DM group) and 30 healthy volunteers (normal control group) were enrolled in the present study. Dual-echo magnetic resonance (MR)(More)
Stream accelerator is a kind of high performance application-specific cooperative processor. Typical stream processor for media processing addresses supporting regular stream. Thus software-managed memory structure, such as Vector/Stream Register File, is designed. With the extension of application domain, hardware-managed memory structure such as cache(More)
Bayesian inference is one of the most important methods for estimating phylogenetic trees in bioinformatics. Due to the potentially huge computational requirements, several parallel algorithms of Bayesian inference have been implemented to run on CPU-based clusters, multicore CPUs, or small clusters of CPUs and GPUs. To the best of our knowledge, however,(More)
— In this paper we consider the modeling and (robust) control of a DC-DC boost converter. In particular, we derive a mathematical model consisting of a constrained switched differential inclusion that includes all possible modes of operation of the converter. The obtained model is carefully selected to be amenable for the study of various important(More)
This paper describes a new hybrid speed regulating method based on improved Fuzzy-PID, which is used in the speed loop for speed and current closed loop control direct current (DC) motor control system. The specific way of the hybrid method depends on the value of the error between reference speed and actual speed when it is bigger than threshold value, the(More)
This article presents two high-efficient parallel realizations of the context-based adaptive variable length coding (CAVLC) based on heterogeneous multicore processors. By optimizing the architecture of the CAVLC encoder, three kinds of dependences are eliminated or weaken, including the context-based data dependence, the memory accessing dependence and the(More)