Learn More
This paper presents the design, implementation, and verification of the Active Cache Emulator (ACE), a novel FPGA-based emulator that models an L3 cache actively and in real-time. ACE leverages interactions with its host system to model the target system (i.e. hypothetical system under study). Unlike most existing FPGA-based cache emulators that collect(More)
This paper introduces the X32V configurable processor core. X32V is geared towards low-power, low-memory embedded systems, such as cell phones, PDAs, and digital cameras. X32V uses a feature that allows for variable length instructions that ultimately decrease the amount of program memory required for applications. In addition, X32V supports additional(More)
  • 1