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This paper presents the design, implementation, and verification of the Active Cache Emulator (ACE), a novel FPGA-based emulator that models an L3 cache actively and in real-time. ACE leverages interactions with its host system to model the target system (i.e. hypothetical system under study). Unlike most existing FPGA-based cache emulators that collect(More)
The performance of a computer system like any other systems is affected by its weakest component. As the latency difference between CPU and memory continues to grow, memory subsystems are becoming the main bottleneck that effectively dictates the performance of the entire system. The criticality of such a problem has been evident from the plethora of(More)
This paper introduces the X32V configurable processor core. X32V is geared towards low-power, low-memory embedded systems, such as cell phones, PDAs, and digital cameras. X32V uses a feature that allows for variable length instructions that ultimately decrease the amount of program memory required for applications. In addition, X32V supports additional(More)
Processors are becoming increasingly complex with many instructions executing in parallel. In order to maintain a high rate of performance there needs to be a minimization of dependencies to exploit Instruction Level Parallelism (ILP). However, there are many hazards that a processor must overcome in order to increase its execution rate. In order to(More)
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