Juin-Yeu Zu

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Extending VLSI CAD with higher-order logic integrates formal veriication with synthesis. The be-neets of doing so are: 1) relating instruction-set descriptions to implementations, 2) designing at a higher level of abstraction than at the level of schematics, 3) verifying by proof, 4) reusing veriied parameterized designs, 5) automatically compiling designs(More)
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