Judit Freijedo

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In nanoscale FPGAs, variability and aging significantly limit performance. In this paper, a novel aging monitoring methodology for FPGA-based designs to mitigate those effects is proposed. Local sensors are embedded in the configured functionality, monitoring critical paths, at production or during product lifetime. No design freeze (slice and routing(More)
The objective of this paper is to propose a performance failure prediction methodology for FPGA-based designs, based on the use of a novel built-in programmable delay sensor. Digital Clock Managers (DCM) is used to fine tune the unsafe observation interval. The design procedure is described, including the constrained placement of some delay sensors. The(More)
— The purpose of this paper is to present a new robust methodology for synchronous communications in a BUS, connecting multi-clock domains. Traditionally, when robust solutions are needed, an asynchronous communication is used. However, the low transfer rates associated with asynchronous solutions make them inadequate for high performance digital systems.(More)
We present a configurable standard platform devoted to measure the dependability of systems-on-chip (SoC) when operating in electromagnetic (EM) environments. The platform is composed of two boards compliant with the 62.132-2 and 62.132-4 IEC Std Parts, being conceived for radiated and conducted measurements, respectively. The SoC under test can be laid(More)
As IC technology scales down, power supply instability may dramatically contribute to signal integrity loss. In this paper, the authors propose a new methodology to enhance circuit tolerance to power-supply voltage (V<sub>DD1</sub>) local variations, without degrading its performance. The underlying idea is to add additional tolerance to the edge trigger of(More)