Jucemar Monteiro

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As the interconnections dominate the circuit delay in nanometer technologies, placement plays a major role to achieve timing closure since it is a main step that defines the interconnection lengths. In initial stages of the physical design flow, the placement goal is to reduce the total wirelength, however total wirelength minimization only roughly(More)
——Energy-efficient fast adders are needed in the design of battery-powered portable devices. Although many fast adder architectures exist, most of them require transistor-level optimizations that prevent their synthesis in a standard-cell flow. This paper presents two energy-efficient Add-One Carry-Select Adders (A1CSA and A1CSAH) suited for standard-cells(More)
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