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- Ju-wook Jang, Viktor K. Prasanna
- IPPS
- 1992

- Ju-wook Jang, Seonil B. Choi, Viktor K. Prasanna
- IEEE Trans. VLSI Syst.
- 2005

We develop new algorithms and architectures for matrix multiplication on configurable devices. These have reduced energy dissipation and latency compared with the state-of-the-art field-programmable gate array (FPGA)-based designs. By profiling well-known designs, we identify “energy hot spots,” which are responsible for most of the energy dissipation.… (More)

- Ju-wook Jang, Seonil B. Choi, Viktor K. Prasanna
- FPT
- 2002

We develop new algorithms and architectures for matrix multiplication on configurable hardware. These designs significantly reduce the latency as well as the area. Our designs improve the previous designs in [7] and [1] in terms of the area/speed metric where the speed denotes the maximum achievable running frequency. The area/speed metrics for the designs… (More)

- Ju-wook Jang, Heonchul Park, Viktor K. Prasanna
- IEEE Trans. Pattern Anal. Mach. Intell.
- 1995

In this paper, we present techniques for energy-efficient design at the algorithm level using FPGAs. We then use these techniques to create energy-efficient designs for two signal processing kernel applications: fast Fourier transform (FFT) and matrix multiplication. We evaluate the performance, in terms of both latency and energy efficiency, of FPGAs in… (More)

- Ju-wook Jang, Madhusudan Nigam, Viktor K. Prasanna, Sartaj Sahni
- IEEE Trans. Parallel Distrib. Syst.
- 1997

The reconfigurable mesh consists of an array of processors interconnected by a reconfigurable bus system. The bus system can be used to dynamically obtain various interconnection patterns among the processors. Recently, this model has attracted a lot of attention. In this paper, we show O(1) time solutions to the following computational geometry problems on… (More)

- Ju-wook Jang, Seonil B. Choi, Viktor K. Prasanna
- FPL
- 2002

- Ju-wook Jang, Heonchul Park, Viktor K. Prasanna
- SPDP
- 1992

An O(1) time algorithm to multiply two N-bit binary numbers using an N ¥ N bit-model of reconfigurable mesh is shown. It uses optimal mesh size and it improves previously known results for multiplication on the reconfigurable mesh. The result is obtained by using novel techniques for data representation and data movement and using multidimensional Rader… (More)

- Seonil B. Choi, Ju-wook Jang, Sumit Mohanty, Viktor K. Prasanna
- The Journal of Supercomputing
- 2003

Reconfigurable architectures such as FPGAs are flexible alternatives to DSPs or ASICs used in mobile devices for which energy is a key performance metric. Reconfigurable architectures offer several design parameters such as operating frequency, precision, amount of memory, degree of parallelism, etc. These parameters define a large design space that must be… (More)

- Chang-hyeon Lim, Ju-wook Jang
- EURASIP J. Wireless Comm. and Networking
- 2009