Joseph Sylvester Chang

Learn More
In this paper, two short-time spectral amplitude estimators of the speech signal are derived based on a parametric formulation of the original generalized spectral subtraction method. The objective is to improve the noise suppression performance of the original method while maintaining its computational simplicity. The proposed parametric formulation(More)
We describe a 16-channel critical-like spaced, high stopband attenuation ( 60 dB, 109th 16-order), micropower (247.5 W@1.1 V, 0.96 MHz), small integrated circuit (IC) area (1.62 mm@0.35m CMOS) finite impulse response filter bank core for power-critical hearing aids. We achieve the low-power and small IC area attributes by our proposed common(More)
In this paper, a fine-grained power gating technique for an asynchronous-logic pipeline stage is proposed using locally controlled gating transistors. The proposed power gating technique is implemented with minimal control overheads (one additional inverter per pipeline stage for driving PMOS Gating) and delay overheads (within 15% more than the(More)
This paper presents an analytical modeling of the mechanisms of total harmonic distortion (THD) of second-order based single-feedback and double-feedback Class-D amplifiers (CDAs). We show that the overall THD in these closed-loop CDAs comprises the THD of their open-loop counterparts reduced by the Loop Gain 1 and the THD due to the combined phase and duty(More)
Class D amplifiers (amps) are conventionally designed as feedforward circuits primarily due to the difficulty of feeding back the digital pulse width modulated output. We analytically investigate the design of Class D amps with feedback and propose a feedback circuit design. We show that the performance of current-art low-power (mWs) low-voltage (1.11.4V)(More)
We propose an asynchronous-logic (async) QuasiDelay-Insensitive (QDI) Static Logic Transistor-level Implementation (SLTI) approach for low power sub-threshold operation. The approach is implemented to design 32-bit pipelined Arithmetic and Logic Units (ALUs), the primary computation core for microprocessors, and benchmarked against the reported Pre-Charged(More)
We describe the design of a micropower digital pulsewidth modulator (PWM) for a hearing instrument Class D amplifier. The PWM embodies a novel delta-compensation ( C) sampling process and a novel pulse generator. The C process is sampled at the same low rate as reported algorithmic sampling processes and it features a similar low total harmonic distortion(More)