Joseph Natonio

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This paper presents a 16-Gb/s 45-nm SOI CMOS transceiver for multi-standard backplane applications. The receiver uses a 12-tap DFE with circuit refinements for supporting higher data rates. Both the receiver and the transmitter use dynamic adaptation to combat parameter drift due to changing supply and temperature. A 3-tap FFE is included in the(More)
This paper describes a wide-range programmable frequency synthesizer building block for 4.25Gbps serial link applications. A unique feature of the design is the use of variable gain charge pumps to adjust loop gain as well as damping in order to minimize output jitter. The synthesizer architecture includes pre and post dividers to maximize programmability.(More)
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