Joseph Jezak

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In this paper we describe a novel clutter cancellation platform based on a two stage approach that combines a feedback guided predictive front-end hybrid clutter canceller with high performance back-end filtering and target detection. The front-end architecture is based on an FPGA implementation of a Kalman filter that predicts target locations in real time(More)
We characterize the impact of the Cell Broadband Engine architecture, on commonly used radar DSP algorithms. We use the capabilities of the CBE to accelerate several key computational kernels including Matrix Multiplication, Matrix Inversion, and the Finite Impulse Response (FIR) filter. These algorithms are implemented and benchmarked as library routines(More)
In this paper, we describe a scalable interconnection network architecture intended for very large multicore processors implemented on stacked chip 3D integrated circuits (3D-IC). These networks provide fully interconnected, low latency, single hop performance with wiring complexity that scales linearly with the size of the network. The enabling technology(More)
In this paper we describe an extension to the MATLAB Phased Array Toolkit that adds a configurable clutter object to model clutter signals returned along a specified signal path. The clutter model is based on the Simkins Unified Clutter Model[1]. The current implementation supports sea clutter in any of five sea states with configurable polarization,(More)
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