direct digital synthesis (DDS) for chirp generation is presented. The radar chip, including receiver, transmitter, quadrature DDS, phase-locked loop (PLL) and analog to digital converter (ADC), has been implemented in a 0.13μm BiCMOS technology. The stretch processing technique is employed to translate the time interval between the received and the… (More)
chip consumes 326 mW in the receive mode and 333 mW in the transmit mode, respectively.
—A quadrature 650 MHz direct digital frequency synthesizer (DDFS) with linear phase and frequency modulation capabilities is realized in a 130nm BiCMOS process. The DDFS supports stretch processing pulse compression for a single chip radar transceiver (RoC). The design features a partial dynamic rotation (PDR) Cordinate Rotation DIgital Computer (CORDIC)… (More)