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Introduction This standard describes a standard syntax and semantics for SystemC synthesis. It defines the subset of SystemC that is suitable for RTL/behavioral synthesis and defines the semantics of that subset for the synthesis domain. This standard is based on the C++ standard and the IEEE 1666 SystemC standard. The purpose of this standard is to define(More)
Notices Accellera Systems Initiative (Accellera) Standards documents are developed within Accellera by the Technical Committee and its Working Groups. Accellera develops its standards through a consensus development process, approved by its members and board of directors, which brings together volunteers representing varied viewpoints and interests to(More)
Keeping up with the increase in system design complexityrequires the deployment of extensive engineeringre-use technologies [15], so-called platform-based designtechniques [8]. When creating derivatives of such a complexsystems-on-chip (SOC) platform, verification represents70% of the overall cost. In this process, functionalverification has become a huge(More)
The increasing power consumption due to the high integration rate of VLSI digital CMOS circuits has become a major concern. In order to reduce the power consumption in integrated circuits, low power techniques have to be applied at all levels of the design flow. Fast and accurate power estimation is needed early in the design process, since power reduction(More)
We present a reusable test infrastructure for RTL designs as an application of mixed-level and mixed-language integration using the IP-XACT standard. The test infrastructure is configurable, meaning that specific configurations can be generated from a template. The main part of the components in the test infrastructure is implemented using the SystemC TLM2(More)
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