José Turrent Figueras

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Reducing leakage in memories is critical to reduce static power consumption in nanometric technologies. A wide-spread technique for reducing the leakage consists of lowering the supply voltage on the SRAM module. The paper investigates the effect of lowering the supply voltage on the robustness of a 6T SRAM cell, both in saturation and sub-threshold(More)
Interconnecting lines with full open defects become floating lines. In nanometric CMOS technologies, gate tunnelling leakage currents impact the behaviour of these lines, which cannot be considered electrically isolated anymore. The voltage of the floating node is determined by its neighbours and leakage currents. After some time an equilibrium is reached(More)
Increased process variations in nano-scaled technologies lead to parametric failures in embedded SRAMs. The reduction of the supply voltage in order to ensure low leakage power leads to a decrease in robustness. These are the main factors which affect the failure probability and so the circuit yield. A widely used technique to determine the failure(More)
Background. The relationship and behavior of serum imunoglobulin E (IgE) level, peripheral blood mononuclear cell (PBMC) human leukocyte antigen DR (HLA-DR) expression and erythrocyte glutathione antioxidant pathway in asthma patients treated with systemic ozone therapy, have not been studied before. Methods. Asthma patients were treated about 1 year with(More)
As technology is scaled down in the nanometric dimensions of the devices, the variability of the manufacturing process on the circuit parameters becomes critical. In addition, environmental changes in power supply voltages and temperature on chip gradients add new uncertainties on future electronic circuits and systems. The VLSI design paradigms are to be(More)
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