José G. Delgado-Frias

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Piece-wise first- and second-order approximations are employed to design commonly used elementary function generators for neural-network emulators. Three novel schemes are proposed for the first-order approximations. The first scheme requires one multiplication, one addition, and a 28-byte lookup table. The second scheme requires one addition, a 14-byte(More)
This paper describes a new approach to implement Dynamically Allocated Multi-Queue (DAMQ) switching elements using a technique called "self-compacting buffers". This technique is efficient in that the amount of hardware required to manage the buffers is relatively small; it offers high performance since it is an implementation of a DAMQ. The first part of(More)
To detect misbehavior on data and mitigate adverse effects, we propose and evaluate a MultipAth Routing Single path transmission (MARS) scheme. The MARS combines multipath routing, single path data transmission, and end-to-end feedback mechanism together to provide more comprehensive protection against misbehavior from individual or cooperating misbehaving(More)
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fine-grain flexibility. More recent coarse-grain reconfigurable architectures are optimized for word-length computations. We have developed a medium-grain reconfigurable(More)
The specific characteristics of mobile ad hoc networks (MANETs) make cooperation among all nodes and secure transmission important issues in its research. Misbehaving nodes with different intentions and capabilities would conduct various types of misbehavior in the networks. In this paper, we present and evaluate a scheme, in which multipath routing(More)