Learn More
Piece-wise first- and second-order approximations are employed to design commonly used elementary function generators for neural-network emulators. Three novel schemes are proposed for the first-order approximations. The first scheme requires one multiplication, one addition, and a 28-byte lookup table. The second scheme requires one addition, a 14-byte(More)
—Reconfigurable hardware contains an array of programmable cells and interconnection structures. Field-pro-grammable gate arrays use fine-grain cells that implement simple logic functions. Some proposed reconfigurable architectures for digital signal processing (DSP) use coarse-grain cells that perform 16-b or 32-b operations. A third alternative is to use(More)
This paper describes a novel reconfigurable architecture for digital signal processing (DSP). The architecture consists of a two-level array of cells and interconnections. DSP algorithms are divided into 4-bit units and mapped onto the first level of cells. Each cell uses a 4x4 matrix of small elements to implement the basic operations required by the(More)