José G. Delgado-Frias

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Piece-wise first- and second-order approximations are employed to design commonly used elementary function generators for neural-network emulators. Three novel schemes are proposed for the first-order approximations. The first scheme requires one multiplication, one addition, and a 28-byte lookup table. The second scheme requires one addition, a 14-byte(More)
This paper describes a novel reconfigurable architecture for digital signal processing (DSP). The architecture consists of a two-level array of cells and interconnections. DSP algorithms are divided into 4-bit units and mapped onto the first level of cells. Each cell uses a 4x4 matrix of small elements to implement the basic operations required by the(More)
This paper describes a new approach to implement Dynamically Allocated Multi-Queue (DAMQ) switching elements using a technique called "self-compacting buffers". This technique is efficient in that the amount of hardware required to manage the buffers is relatively small; it offers high performance since it is an implementation of a DAMQ. The first part of(More)
In this paper we introduce a VLSI priority encoder that uses a novel priority lookahead scheme to reduce the delay for the worse case operation of the circuit, while maintaining a very low transistor count. The encoder's topmost input request has the highest priority ; this priority descends linearly. Two design approaches for the priority encoder are(More)