José Cruz-Rivera

Learn More
This paper introduces Pica, a fine-grain, message passing architecture designed to efficiently support high-throughput parallel applications. This focus on high-throughput applications allows a small local memory of 4096 36-bit words. The architecture minimizes overhead for basic parallel operations. An operand-addressed context cache and round-robin task(More)
Real-time image processing applications have tremendous computational workloads and I/O throughput requirements. Operation in mobile, portable devices poses stringent resource limitations (size, weight, and power). The SIMD Pixel Processor (SIMPil) has been designed at Georgia Tech to address these problems. In SIMPil, an image sensor array (focal plane) is(More)
Recent architectural and technological advances have led to the feasibility of a new class of massively parallel processing systems based on a fine-grain, message-passing computational model. These machines provide a new alternative for the development of fast, cost-efficient Maximum Likelihood-Expectation Maximization (ML-EM) algorithmic formulations. As(More)
—Three-dimensional packaging technologies are critical for enabling ultra-compact, massively parallel processors (MPPs) for embedded applications. Through-wafer optical interconnect has been proposed as a useful technology for building ultra-compact MPPs since it provides a simplified mechanism for interconnecting stacked multichip substrates. This paper(More)
This paper introduces a new network topology, the ooset-cube, for three-dimensional image processing systems. It provides general node-to-node communications for random message traac with an average latency that is comparable to a k-ary 3-cube. It is well suited for communication patterns common in image processing applications (e.g., image scaling,(More)
The rapid advance of VLSI and packaging technologies has a significant impact on system architecture. In this paper, an analytical model is used to explore the design space of interconnection networks for a 4,096 node processing system incorporating multi-node chips packaged on a single MCM substrate. Possible designs are evaluated for a two-level(More)
  • 1