José Cruz-Rivera

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Three-dimensional packaging technologies are critical for enabling ultra-compact, massively parallel processors (MPPs) for embedded applications. Through-wafer optical interconnect has been proposed as a useful technology for building ultra-compact MPPs since it provides a simplified mechanism for interconnecting stacked multichip substrates. This paper(More)
Real-time image processing requires high computational and I/O throughputs obtained by use of optoelectronic system solutions. A novel architecture that uses focal-plane optoelectronic-area I/O with a fine-grain, low-memory, single-instruction-multiple-data (SIMD) processor array is presented as an efficient computational solution for real-time(More)
Recent architectural and technological advances have led to the feasibility of a new class of massively parallel processing systems based on a fine-grain, message-passing computational model. These machines provide a new alternative for the development of fast, cost-efficient Maximum Likelihood-Expectation Maximization (ML-EM) algorithmic formulations. As(More)
Real-time image processing applications have tremendous computational workloads and I/O throughput requirements. Operation in mobile, portable devices poses stringent resource limitations (size, weight, and power). The SIMD Pixel Processor (SIMPil) has been designed at Georgia Tech to address these problems. In SIMPil, an image sensor array (focal plane) is(More)
Future military scenarios will rely on advanced imaging sensor technology beyond the visible spectrum to gain total battlefield awareness. Real-time processing of these data streams requires tremendous computational workloads and I/O throughputs. This paper presents three applications for hyper-spectral data streams, vector quantization, region autofocus,(More)
This paper introduces Pica, a fine-grain, message passing architecture designed to efficiently support high-throughput parallel applications. This focus on high-throughput applications allows a small local memory of 4096 36-bit words. The architecture minimizes overhead for basic parallel operations. An operand-addressed context cache and round-robin task(More)
The rapid advance of VLSI and packaging technologies has a significant impact on system architecture. In this paper, an analytical model is used to explore the design space of interconnection networks for a 4,096 node processing system incorporating multi-node chips packaged on a single MCM substrate. Possible designs are evaluated for a two-level(More)
Recent architectural and technological advances have led to the feasibility of a new class of massively parallel processing systems based on a fine-grain, message-passing computational model. These machines provide a new alternative for the development of fast, cost-emcient Maximum Likelihood-Expectation Maximization (ML-EM) algorithmic formulations. As an(More)
Smart pixel architectures offer important new opportunities for low cost, portable image processing systems. They provide greater I/O bandwidth and computing performance than systems based on CCD and microprocessors. However, finding a balance between performance, flexibility, efficiency, and cost depends on an evaluation of target applications. This paper(More)