José Carlos S. Palma

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This work investigates the reduction of power consumption in networks-on-chip through the reduction of transition activity using data coding schemes. Power macromodels for NoC and encoding modules were built, allowing the estimation of the power consumption as a function of the transition activity at each module input. Power macromodels are embedded in a(More)
This work addresses the problem of application mapping in networks-on-chip (NoCs), having as goal to minimize the total dynamic energy consumption of complex system-on-a-chips (SoCs). It explores the importance of characterizing network traffic to predict NoC energy consumption and of evaluating the error generated when the bit transitions influence on(More)
This paper describes the implementation of a passive RFID tag targeting low power implementation, which works on 915 MHz UHF frequency. The proposed architecture allows customizing the command sets implemented inside its digital block, according to the target application needs, saving area and reducing power consumption. A flexible design flow is proposed(More)
This work addresses the problem of application mapping in networks-on-chip (NoCs). It explores the importance of characterizing network traffic to effectively predict NoC energy consumption. Traffic is seen as an important factor affecting the problem of mapping applications into NoCs having as goal to minimize the total dynamic energy consumption of a(More)
This work investigates the reduction of power consumption in Networks-on-Chip (NoCs) through the reduction of transition activity using data coding schemes developed for bus-based systems and proposes a new coding scheme suitable for NoC-based systems. The estimation of the NoC power consumption was performed with basis on macromodels which reproduce the(More)
This work describes the implementation of digital reconfigurable systems (DRS) using commercial FPGA devices. The main goal is to present a set of tools for remote and partial reconfiguration developed for the Virtex FPGA family. Even though the tools are targeted to a specific device, their building principles may easily be adapted to other FPGA families,(More)
This work addresses the problem of power consumption in networks-on-chip (NoCs). It investigates the reduction of dynamic power consumption through the reduction of transition activity using data coding techniques. Power macromodels for various NoC modules were built, allowing the estimation of the power consumption as a function of the transition activity(More)
This paper describes the implementation of a passive low power tag, which works on 915 MHz UHF frequency. The tag implements an innovative and efficient synchronization algorithm, which deals with significant reference clock variations. A flexible design flow is proposed for the customization, verification and synthesis of the digital block, targeting low(More)
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