Jorge Fernandez-Berni

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This paper reports a 176×144-pixel smart image sensor designed and fabricated in a 0.35µm CMOS-OPTO process. The chip implements a massively parallel focal-plane processing array which can output different simplified representations of the scene at very low power. The array is composed of pixel-level processing elements which carry out analog image(More)
—This paper reports a multi-layered smart image sensor architecture for feature extraction based on detection of interest points. The architecture is conceived for 3D IC technologies consisting of two layers (tiers) plus memory. The top tier includes sensing and processing circuitry aimed to perform Gaussian filtering and generate Gaussian pyramids in fully(More)
—Cellular Nonlinear Networks (CNN) establish a theoretical framework in which programmable focal-plane image processing arrays can be developed. The conventional support for its analog programmability in VLSI is the implementation of transconductor-based multiplication of the input, output and state variables times the corresponding template elements.(More)
—This paper introduces a CMOS vision sensor to extract the Gaussian pyramid with an energy cost of 26.5 nJ/px at 2.64 Mpx/s, thus outperforming conventional solutions employing an imager and a separate digital processor. The chip, manufactured in a 0.18 μm CMOS technology, consists of an arrangement of 88 × 60 processing elements (PEs) which captures images(More)
— Incorporating multi-resolution capabilities into im-agers renders additional power saving mechanisms in the subsequent image processing. In this paper, we show how, by exploiting a certain mask structure, 3 × 3 kernels can be reduced to 2 × 2 kernels if charge redistribution is provided at the focal plane of the imaging device. More precisely, by(More)
—This paper presents Wi-FLIP, a vision-enabled WSN node resulting from the integration of FLIP-Q, a prototype vision chip, and Imote2, a commercial WSN platform. In Wi-FLIP, image processing is not only constrained to the digital domain like in conventional architectures. Instead, its image sensor — the FLIP-Q prototype — incorporates pixel-level processing(More)
—This live demonstration showcases the Gaussian pyramid with a CMOS vision sensor. The chip features a 176 × 120 pixel array in standard 0.18 µm CMOS technology. The sensing elements are designed as 3-Transistor Active Pixel Sensors (3T-APS) with in-pixel ADC and CDS. The Gaussian pyramid is extracted concurrently with a double-Euler switched-capacitor(More)
Privacy awareness constitutes a critical aspect for smart camera networks. An ideal flawless protection of sensitive information would boost their application scenarios. However, it is still far from being achieved. Numerous challenges arise at different levels, from hardware security to subjective perception. Generally speaking, it can be stated that the(More)