Jorge Echavarria

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In this paper, we propose a novel approximate adder structure for LUT-based FPGA technology. Compared with a full featured accurate carry-ripple adder, the longest path is significantly shortened which enables the clocking with an increased clock frequency. By using the proposed adder structure, the throughput of an FPGA-based implementation can be(More)
This paper proposes an improved procedure to watermark soft Intellectual Property (IP) Cores at the Register Transfer Level (RTL) using Genetic Algorithms (GA). In order to merge the watermark signature and the IP Core's behavioral description, both are translated into Finite State Machines (FSM). The resulting FSM contains the watermarked IP Core(More)
Approximate Computing aims at trading off computational accuracy against improvements regarding performance, resource utilization and power consumption by making use of the capability of many applications to tolerate a certain loss of quality. A key issue is the dependency of the impact of approximation on the input data as well as user preferences and(More)
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