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Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration
TLDR
This article proposes field programmable gate array-based scalable architecture for discrete cosine transform (DCT) computation using dynamic partial reconfiguration, and shows the experimental results and comparisons between different configurations using both partial reconfigured and nonpartial reconfigured configurations.
View on ACM
A Self-Reconfigurable Platform for Scalable DCT Computation Using Compressed Partial Bitstreams and BlockRAM Prefetching
TLDR
A self-reconfigurable platform which can reconfigure the architecture of DCT computations during run-time using dynamic partial reconfiguration using a configuration manager implemented in the embedded processor.
View on IEEE
Fault Demotion Using Reconfigurable Slack (FaDReS)
TLDR
An active dynamic redundancy-based fault-handling approach exploiting the partial dynamic reconfiguration capability of static random-access memory-based field-programmable gate arrays achieves an improved recovery in a bounded number of reconfigurations.
View on IEEE
Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties
TLDR
The proposed architecture based on the recursion equation provides optimum balance in both hardware complexity and throughput rate when compared with other 2-D IDCT architectures.
View on IEEE
A scalable H.264/AVC deblocking filter architecture using dynamic partial reconfiguration
TLDR
A scalable H.264/AVC deblocking filter architecture based on FPGA using dynamic partial reconfiguration that can easily support the required computing capability for different resolutions and frame rates of video sequences is presented.
View on IEEE
Efficient VLSI architecture for video transcoding
TLDR
This paper shows how different core algorithms can be mapped onto the same hardware fabric and can be executed through the pre-defined PEs and demonstrates that high throughput rate can be achieved for IDCT and DCT-MC by fully utilizing the sparseness property of DCT coefficient matrix.
View on IEEE
Reconfigurable Architecture for ZQDCT Using Computational Complexity Prediction and Bitstream Relocation
TLDR
A hybrid model-based quality priority algorithm is developed to reduce power consumption, required hardware resources, and computation time with a small quality degradation in ZQDCT computation.
View on IEEE
Dynamic Partial Reconfiguration Approach to the Design of Sustainable Edge Detectors
Evolutionary refurbishment of faulty modules by means of intrinsic Genetic Algorithms (GAs) is also utilized when the system performance declines below a pre-defined threshold. Finally, dynamic…
Self-Adapting Resource Escalation for Resilient Signal Processing Architectures
TLDR
The results indicate the benefits of priority-aware resiliency over conventional redundancy in terms of fault-recovery, power consumption, and resource-area requirements.
View on Springer
Efficient VLSI implementation of inverse discrete cosine transform [image coding applications]
TLDR
A novel 2D IDCT architecture, based on the energy compaction property of the 2D DCT, is proposed, which achieves a high throughput rate and provides an efficient way to control the trade-off between visual quality of the reconstructed image and computational complexity.
View on IEEE
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