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A 512Gb 3b/Cell 7th -Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface
  • Jiho Cho, D. Chris Kang, +41 authors Jaihyuk Song
  • Computer Science
  • IEEE International Solid- State Circuits…
  • 13 February 2021
TLDR
This work integrated the peripheral circuits below the cell array as introduced in [2], and to cope with lower metal-contact height, a novel structure for the capacitor device was used to maximize capacitance per unit area. Expand
Lateral-Extended (LatEx.) active for improvement of data retention time for sub 60nm DRAM era
A new active isolation structure, LatEx (lateral-extended) active, which exploits recess channel transistors, is proposed. By realizing the LatEx active, data retention time enhancement wasExpand