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The influence of the internal circuit layout on the chip CDM performance is reported in this paper. It is found that the well pick-up has great impact on the chip CDM performance. The well pick-up can sink the CDM current into the P-Well and induce the non-uniform current to stress the device. This paper also verifies that the bus-line capacitors are more(More)
—This paper identifies and investigates a new source of random threshold voltage variation, which is referred to as Grain-Orientation-induced Quantum Confinement (GOQC) in emerging ultra-thin-body metal-gate complementary metal– oxide–semiconductor (CMOS) devices including FinFET, tri-gate, and nanowire field-effect transistors. Due to the dependence of the(More)
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