Jone F. Chen

  • Citations Per Year
Learn More
The influence of the internal circuit layout on the chip CDM performance is reported in this paper. It is found that the well pick-up has great impact on the chip CDM performance. The well pick-up can sink the CDM current into the P-Well and induce the non-uniform current to stress the device. This paper also verifies that the bus-line capacitors are more(More)
The reliability and performance of NMOSFET asymmetric LDD devices (with no LDD on the source side) are compared with that of conventional LDD devices. The results show that asymmetric LDD devices exhibit higher Idsat and larger Isub . To maintain the same hot-carrier lifetime, asymmetric LDD devices must operate at lower Vdd . For the same hot-carrier(More)
Enhanced hot-carrier induced current degradation in narrow channel PMOSFET’s with shallow trench isolation structure is observed. This phenomenon is not due to the increase in gate current, but the result of the increase in the electron trapping efficiency of the gate oxide. Mechanical stress may be responsible for the enhanced electron trapping efficiency.
This paper identifies and investigates a new source of random threshold voltage variation, which is referred to as Grain-Orientation-induced Quantum Confinement (GOQC) in emerging ultra-thin-body metal-gate complementary metal– oxide–semiconductor (CMOS) devices including FinFET, tri-gate, and nanowire field-effect transistors. Due to the dependence of the(More)
  • 1