Jonathan Woodruff

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The processes that control the formation, intensity and track of hurricanes are poorly understood. It has been proposed that an increase in sea surface temperatures caused by anthropogenic climate change has led to an increase in the frequency of intense tropical cyclones, but this proposal has been challenged on the basis that the instrumental record is(More)
Atlantic tropical cyclone activity, as measured by annual storm counts, reached anomalous levels over the past decade. The short nature of the historical record and potential issues with its reliability in earlier decades, however, has prompted an ongoing debate regarding the reality and significance of the recent rise. Here we place recent activity in a(More)
Contemporary CPU architectures conflate virtualization and protection , imposing virtualization-related performance, programma-bility, and debuggability penalties on software requiring fine-grained protection. First observed in micro-kernel research, these problems are increasingly apparent in recent attempts to mitigate software vulnerabilities through(More)
—This paper presents a cache tracker, a hardware component to track the cache state of hundreds of caches serving processors modeled using threads on a single MIPS64 processor. This host-multithreading approach allows a single, low-cost FPGA to model large systems to allow quick and broad architectural exploration with reasonable simulation performance. The(More)
Motivated by contemporary security challenges, we reevaluate and refine capability-based addressing for the RISC era. We present CHERI, a hybrid capability model that extends the 64-bit MIPS ISA with byte-granularity memory protection. We demonstrate that CHERI enables language memory model enforcement and fault isolation in hardware rather than software,(More)
CHERI extends a conventional RISC Instruction-Set Architecture, compiler, and operating system to support fine-grained, capability-based memory protection to mitigate memory-related vulnerabilities in C-language TCBs. We describe how CHERI capabilities can also underpin a hardware-software object-capability model for application compartmentalization that(More)
We propose a new memory-safe interpretation of the C abstract machine that provides stronger protection to benefit security and debugging. Despite ambiguities in the specification intended to provide implementation flexibility, contemporary implementations of C have converged on a memory model similar to the PDP-11, the original target for C. This model(More)
The future impacts of climate change on landfalling tropical cyclones are unclear. Regardless of this uncertainty, flooding by tropical cyclones will increase as a result of accelerated sea-level rise. Under similar rates of rapid sea-level rise during the early Holocene epoch most low-lying sedimentary coastlines were generally much less resilient to storm(More)
SRI International is acknowledged as an additional copyright holder Technical reports published by the University of Cambridge Computer Laboratory are freely available via the Internet: Abstract This document describes the rapidly maturing design for the Capability Hardware Enhanced RISC Instructions (CHERI) Instruction-Set Architecture (ISA), which is(More)