Jonathan A. Winter

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Future many-core microprocessors are likely to be heterogeneous, by design or due to variability and defects. The latter type of heterogeneity is especially challenging due to its unpredictability. To minimize the performance and power impact of these hardware imperfections, the runtime thread scheduler and global power manager must be nimble enough to(More)
In future large-scale multi-core microprocessors, hard errors and process variations will create dynamic heterogeneity, causing performance and power characteristics to differ among the cores in an unanticipated manner. Under this scenario, naive assignments of applications to cores degraded by various faults and variations may result in large performance(More)
Future chip multiprocessors (CMPs) will be capable of deconfiguring faulty units in order to permit continued operation in the presence of wear-out failures. However, the unforeseen downside is pipeline imbalance due to other portions of the pipeline now being overprovisioned with respect to the deconfigured functionality. We propose PowerTransfer, a novel(More)
Future chip multiprocessors (CMPs) will be expected to deliver robust performance in the face of manufacturing process variations and hard errors. While prior research has addressed how to keep these chips functional, these degraded CMPs may still be unusable because of lost performance and power efficiency. The unpredictable nature of the variability and(More)
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