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—This paper proposes an architecture and a synthesis method for high-speed computation of fixed-point numerical functions such as trigonometric, logarithmic, sigmoidal, square root, and combinations of these functions. Our architecture is based on the lookup table (LUT) cascade, which results in a significant reduction in circuit complexity compared to(More)
— The availability of large, inexpensive memory has made it possible to realize numerical functions, such as the reciprocal, square root, and trigonometric functions, using a look-up table. This is much faster than by software. However, a naive look-up method requires unreasonably large memory. In this paper, we show the use of a look-up table (LUT) cascade(More)
We analyze the performance of various heuristic algorithms for minimizing realizations of multiple-valued functions by the newly developed CCD 191 and CMOS [W] programmable logic arrays. The functions realized by such PLA's are in sum-of-products form, where sum is ordinary addition truncated to the highest logic value, and where product represents the MIN(More)
This paper presents an architecture and a synthesis method for programmable numerical function generators of trigono-metric functions, logarithm functions, square root, reciprocal , etc. Our architecture uses an LUT (Look-Up Table) cascade as the segment index encoder, compactly realizes various numerical functions, and is suitable for automatic synthesis.(More)
This paper presents an architecture and a synthesis method for programmable numerical function generators (NFGs) for trigonometric, logarithmic, square root, and reciprocal functions. Our NFG partitions a given domain of the function into non-uniform segments using an LUT cascade, and approximates the given function by a quadratic polynomial for each(More)
With two cosine terms about a third and with three cosine terms about half as many shifts are needed as for an arbitrary 5. The number of additions varies from about a fifth as many at n = 1 to about a fifteenth or sixteenth as many at n = 5. It should be noted that if the processor used to implement this has 4 or 8 bit shifts, the number of shifts is(More)
Multiple-output switching functions can be simulated by multiple-valued d e cision diagrams (MDDs) at a signicant reduction in computation time. We analyze the following approaches to the representation problem: shared multiple-valued decision diagrams (SMDDs), multi-terminal multiple-valued d e ci-sion diagrams (MTMDDs), and shared multi-terminal(More)
—The traditional problem in binary decision diagrams (BDDs) has been to minimize the number of nodes since this reduces the memory needed to store the BDD. Recently, a new problem has emerged: minimizing the average path length (APL). APL is a measure of the time needed to evaluate the function by applying a sequence of variable values. It is of special(More)