#### Filter Results:

- Full text PDF available (101)

#### Publication Year

1973

2017

- This year (2)
- Last 5 years (22)
- Last 10 years (51)

#### Publication Type

#### Co-author

#### Journals and Conferences

#### Key Phrases

Learn More

A logic function f has a disjoint bi-decomposition i f can be represented as f = h(g1(X1); g2(X2)), where X1 and X2 are disjoint set of variables, and h is an arbitrary two-variable logic fuction. f has a non-disjoint bidecomposition i f can be represented as f(X1;X2; x) = h(g1(X1; x); g2(X2; x)), where x is the common variable. In this paper, we show a… (More)

- T. Sasao, J. T. Butler, M. D. Riedel
- 2004

The availability of large, inexpensive memory has made it possible to realize numerical functions, such as the reciprocal, square root, and trigonometric functions, using a lookup table. This is much faster than by software. However, a naive look-up method requires unreasonably large memory. In this paper, we show the use of a look-up table (LUT) cascade to… (More)

- Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler
- IEEE Trans. Computers
- 2007

This paper proposes an architecture and a synthesis method for high-speed computation of fixed-point numerical functions such as trigonometric, logarithmic, sigmoidal, square root, and combinations of these functions. Our architecture is based on the lookup table (LUT) cascade, which results in a significant reduction in circuit complexity compared to… (More)

Minimizing the Average Path Length (APL) in a BDD reduces the time needed to evaluate Boolean functions represented by BDDs. This paper describes an efficient heuristic APL minimization procedure based on BDD variable reordering. The reordering algorithm is similar to classical variable sifting with the cost function equal to the APL rather than the number… (More)

- Tsutomu Sasao, Jon T. Butler
- ISMVL
- 1996

Multiple-output switching functions can be simulated by multiple-valued decision diagrams (MDDs) at a signi cant reduction in computation time. We analyze the following approaches to the representation problem: shared multiple-valued decision diagrams (SMDDs), multi-terminal multiple-valued decision diagrams (MTMDDs), and shared multi-terminal… (More)

- Parthasarathy P. Tirumalai, Jon T. Butler
- IEEE Trans. Computers
- 1991

We analyze the performance of various heuristic algorithms for minimizing realizations of multiple-valued functions by the newly developed CCD 191 and CMOS [W] programmable logic arrays. The functions realized by such PLA’s are in sum-of-products form, where sum is ordinary addition truncated to the highest logic value, and where product represents the MIN… (More)

- Tsutomu Sasao, Jon T. Butler
- ISMVL
- 1994

- C. L. Frenzen, Tsutomu Sasao, Jon T. Butler
- J. Computational Applied Mathematics
- 2010

The introduction of high-speed circuits to realize an arithmetic function f as a piecewise linear approximation has created a need to understand how the number of segments depends on the interval a ≤ x < b and the desired approximation error ε. For the case of optimum non-uniform segments, we show that the number of segments is given as s(ε) ∼ c √ ε , (ε →… (More)

- Edward A. Bender, Jon T. Butler
- IEEE Trans. Computers
- 1978

Expressions are derived for the approximate number of functions realized by various n-variable fanout-free networks. Six recently studied networks are considered. It is shown that the relative number of functions realized by two networks for smal and large n is quite different in certain cases.

- Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
- ASP-DAC
- 2006

This paper presents an architecture and a synthesis method for programmable numerical function generators (NFGs) for trigonometric, logarithmic, square root, and reciprocal functions. Our NFG partitions a given domain of the function into non-uniform segments using an LUT cascade, and approximates the given function by a quadratic polynomial for each… (More)