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This article presents a digitally controlled analog frequency-locked loop used for VCO characterization and test. The proposed scheme allows a frequency tuning better than 8 parts per million (ppm). The AFLL is implemented in 32nm CMOS technology and standard CMOS library cells are used for all the digital blocks. The AFLL comprises a 17-bit frequency(More)
In this work, a digitally assisted frequency locked loop is implemented using 32-nm CMOS technology and acts as a 20-GHz frequency synthesizer. The frequency difference between the reference clock and the VCO output is obtained using a pair of 18- bit counters. Also, an offset value is added to the counter output to tune the VCO frequency in closed loop.(More)
An increase of demand for high-speed communications leads to increasing the requirements for the interface between the digital and analog domains. That is why now design of high-performance analog-to-digital (ADC) and digital-to-analog (DAC) converters becomes so important. A lot of publications are dedicated to enhancement of ADC and DAC performance. For a(More)
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