John V. Woods

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Configuring a million-core parallel system at boot time is a difficult process when the system has neither specialised hardware support for the configuration process nor a pre-configured default state that puts it in operating condition. The architecture of SpiNNaker, a parallel chip multiprocessor (CMP) system for neural network simulation, is in this(More)
—An asynchronous implementation of the ARM microprocessor has been developed using an approach based on Sutherland's Micropipelines [1]. The design allows considerable internal asynchronous concurrency. This paper presents the rationale for the work, the organization of the chip, and the characteristics of the prototype silicon. The design displays unusual(More)
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