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The Clock Divider circuit has found immense application in Multiple Clock Domain (MCD) systems like ASICs, SoC and GALS. In MCD systems, we generate many clock signals of various frequencies from a high frequency clock by frequency division. Power is an important parameter to be minimized since the nodes in a clock divider circuit will toggle at clock(More)
Tree driven mesh is gaining popularity as a viable method to distribute clock with minimum skew in Deep Sub Micron (DSM) technology. In the design of the leaf level mesh, the density of the mesh at various parts of the chip is a crucial factor which decides the clock skew and power dissipated in the mesh. We propose a ca-pacitance driven mesh formation(More)
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