John P. Uyemura

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In this paper a new approach of reducing power for a given system is developed that is self resetting logic, a parallel compressor is developed for multiplier by reducing its power with facilitation of this low power logic technique. By using this technique the power dissipation is significantly reduced with respect to other logics. By implementing the(More)
A senior-level design laboratory course is described, in which an optical fiber communication network is expanded or improved by successive generations of students. In this evolutionary approach, student teams base their work on the final written reports of students in previous course offerings. In addition to its primary goal of providing a high-level(More)
This paper presents a three-stage 1. 8V ring VCO in a 0. 18 ?m CMOS technology with wide tuning range and a good phase noise differential ring oscillator . The oscillator architecture is a three stage differential ring with Multi pass path using pushpull inverters. The circuit was implemented and the measured tuning range of the from 3. 8741 GHz to 5. 913(More)
Photodiodes are integrated into complementary metal-oxide semiconductor very-large-scale integration logic circuits to provide a hybrid interface between parallel-optical and electronic computing formats. This permits direct parallel transfer from an optical processor or storage element to a standard electronic system. The optical input beams may be viewed(More)