John Osenbach

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A model for corrosion induced failure in wire bond devices made with either Cu or Au wire was developed. The model is based on detailed analysis of the chemical composition, crystallography, and micro structure of the corrosion induced failure sites. The detailed analysis was enabled by both a scanning electron microscope (SEM) and a transmission electron(More)
Historically Cu wire has been targeted to lower pin count high power discrete devices and consumer product for a long time. As gold costs increased the industry started focusing on moving more mainstream products to Cu wire. Markets that have seen the largest growth in Cu wire bonded products include consumer electronics, communication devices and(More)
Results of a development program aimed at introducing Cu wire to a low K circuit under pad integrated circuit made in 65nm technology are summarized. The results demonstrate that if the wire bond process is optimized along with the tool design, then it is possible to produce both substrate (PBGA) and lead frame (TQFP) devices with pure Cu wire that show no(More)
The development of a 2L overmolded exposed die flip chip package is summarized in this paper. The development consisted of first completing extensive thermal & mechanical modeling for optimized package thermal & warpage performance. The modeling results were used to define manufacturing requirements including the bill of materials. Because the die(More)
The viability of flip chip packages that incorporate small diameter (65um-80um) Cu pillar bumps on large die (up to 500mm<sup>2</sup>) in large packages (up to 55mm &#x00D7; 55mm) is demonstrated. To do so, bump formation and microstructure must be controlled. In particular, avoidance of bump tearing defects, which were found on assembly with die(More)
Traditionally fan out wafer level package technology has been associated with lower power, smaller body sizes (typically &lt;; 8 mm &#x00D7; 8 mm), small body-to-die size area ratios (&lt;;2) and fine pitch BGAs (0.4 mm or less). This work extends this technology to larger body sizes up to 13 mm &#x00D7; 13 mm, higher powers, &gt; 5 W, and larger(More)
Background New challenges for the electronics industry are being incurred as a result of the global adoption of Pb-free initiatives. The microelectronics packaging sector is particularly impacted by these events as a result of changes to design, material requirements and assembly specifications. Solder alloys and surface finishes for package substrates (and(More)
Manufacture of highly reliable lead free flip chip devices made in 40nm technology has recently been reported by the authors via the use of large test chips in 42.5&#x00D7;42.5mm body size. These test die were designed to ensure that package die interactions as related to degradation of the dielectric and metal stack used in 40nm silicon technology with(More)
Experiments have been completed on dependence of the wire pull strength on aging duration in TCB(Temperature Cycle B), HTS(High Temperature Storage), uHAST(unbiased Highly Accelerated Stress Test), THS(Temperature Humidity Soaking), and PCT(Pressure Cooker Test) for non-molded bare Cu and Pd coated Cu wire bonded devices. The data can be summarized as(More)
The development of a thinner core (:100um) laminate array based exposed die fcCSP package with package to die area ratio &gt; 12, package total height maximum 0.77mm that meets the JEDEC &lt;; &#x00B1;100um warpage requirement is discussed. The same approach used for the 150um thick core exposed die fcCSP technology was used for this work, namely finite(More)