John Oliver

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We present Synchroscalar, a tile-based architecture forembedded processing that is designed to provide the flexibilityof DSPs while approaching the power efficiency ofASICs. We achieve this goal by providing high parallelismand voltage scaling while minimizing control and communicationcosts. Specifically, Synchroscalar uses columnsof processor tiles(More)
Soft errors have become a significant concern and recent studies have measured the " architectural vulnerability factor " of systems to such errors, or conversely, the potential that a soft error is masked by latches or other system behavior. We take soft-error tolerance one step further and examine when an application can tolerate errors that are not(More)
In this paper, we investigate the power implications of tile size selection for tile-based processors. We refer to this investigation as a tile <i>granularity</i> study. This is accomplished by distilling the architectural cost of tiles with different computational widths into a system metric we call the <i>Granularity Indicator</i> (GI). The GI is then(More)
Communication and multimedia applications with increased data rates and enhanced functionality continuously raise the bar for the computational requirements of future microprocessors. In order to meet these computational demands it is necessary to exploit sub-word parallelism efficiently. We propose to make sub-word data movement a first-class operation in(More)
We present an overview of the Synchroscalar single-chip, multi-core processor. Through the design of Synchroscalar, we find that high energy efficiency and low complexity can be attained through parallelization. The importance of adequate inter-core interconnect is also demonstrated. We discuss the impact of having multiple frequency and voltage domains on(More)
Increasingly System-On-A-Chip platforms which incorporate both microprocessors and re-programmable logic are being utilized across several fields ranging from the automotive industry to network infrastructure. Unfortunately, the development tools accompanying these products leave much to be desired, requiring knowledge of both traditional embedded systems(More)
  • San Luis Obispo, John Andres Cadwell, John Andres, Cadwell Jr, Xiao-Hua Yu, John Oliver
  • 2010
In order for an aircraft to remain in stable flight, the center of gravity (CG) of an aircraft must be located in front of the center of lift (CL). As the center of gravity moves rearward, pitch stability decreases and the sensitivity to control input increases. This increase in sensitivity is known as pitch gain variance. Minimizing the pitch gain variance(More)
As circuit geometries continue to shrink, and supply voltages remain relatively constant, circuit wearout becomes a concern. We propose that the relative reliability of the circuits of a processor be exposed to the operating system, and be managed by a credit-based wearout monitor. This wearout monitor receives dynamic updates of the reliability of circuits(More)