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A direct numerical simulation of a turbulent channel flow is performed. The unsteady Navier-Stokes equations are solved numerically at a Reynolds number of 3300, based on thc mean centreline velocity and channel half-width, with about 4 x los grid points (192 x 129 x 160 in 2, y, 2). All essential turbulence scales are resolved on the computational grid and(More)
Future many-core processors will require high-performance yet energy-efficient on-chip networks to provide a communication substrate for the increasing number of cores. Recent advances in silicon nanophotonics create new opportunities for on-chip networks. To efficiently exploit the benefits of nanophotonics, we propose Firefly - a hybrid, hierarchical(More)
Evolving technology and increasing pin-bandwidth motivate the use of high-radix routers to reduce the diameter, latency, and cost of interconnection networks. High-radix networks, however, require longer cables than their low-radix counterparts. Because cables dominate network cost, the number of cables, and particularly the number of long, global cables(More)
Increasing integrated-circuit pin bandwidth has motivateda corresponding increase in the degree or radix of interconnection networksand their routers. This paper introduces the <i>flattened butterfly,</i> a cost-efficient topology for high-radix networks. On benign (load-balanced) traffic, the flattened butterfly approaches the cost/performance of a(More)
On-chip network is becoming critical to the scalability of future many-core architectures. Recently, nanophotonics has been proposed for on-chip networks because of its low latency and high bandwidth. However, nanophotonics has relatively high static power consumption, which can lead to inefficient ar-chitectures. In this work, we propose FlexiShare – a(More)
With the trend towards increasing number of cores in chip multiprocessors, the on-chip interconnect that connects the cores needs to scale efficiently. In this work, we propose the use of high-radix networks in on-chip interconnection net- works and describe how the flattened butterfly topology can be mapped to on-chip networks. By using high-radix routers(More)
—Network-on-Chips (NoCs) are becoming integral parts of modern microprocessors as the number of cores and modules integrated on a single chip continues to increase. Research and development of future NoC technology relies on accurate modeling and simulations to evaluate the performance impact and analyze the cost of novel NoC architectures. In this work, we(More)
Three overlapping pathways mediate the transport of cytoplasmic material to the vacuole in Saccharomyces cerevisiae. The cytoplasm to vacuole targeting (Cvt) pathway transports the vacuolar hydrolase, aminopeptidase I (API), whereas pexophagy mediates the delivery of excess peroxisomes for degradation. Both the Cvt and pexophagy pathways are selective(More)
It is shown, by direct numerical simulations, that the skin-friction drag in a fully developed channel can be sustained below that corresponding to the laminar profile when the flow is subjected to surface blowing and suction in the form of an upstream travelling wave. A key mechanism that induces the sub-laminar drag is the creation of positive (negative)(More)
On-chip networks are critical to the scaling of future multi-core processors. The challenge for on-chip network is to reduce the cost including power consumption and area while providing high performance such as low latency and high bandwidth. Although much research in on-chip network have focused on improving the performance of on-chip networks, they have(More)