—In this paper, we present a methodology for simulating the impact of within-die (die-level) polysilicon critical dimension (poly-CD) variation on circuit performance. The methodology is illustrated on a 0.25 m 64 2 2 2 8 SRAM macrocell layout. For this example, the impact as measured through signal skew is found to be significant and strongly dependent on… (More)
1.0 Abstract Increasing circuit complexity and die area with at the same time decreasing device dimensions render traditional approaches to IC design inadequate. The result is serious risk of suboptimal designs and thus poor performance and/or poor manufacturing yield. New tools are necessary to capture the effects of statistical variability of devices and… (More)
In recent years, Analog design tools have helped reduce the design time for different kinds of custom analog circuits. can synthesize and layout various analog circuits, in about 10 minutes. Due to the strong correlation between yield and profitability, it is important to predict the design yield, and attempt to change the design to improve the yield.… (More)
Power management and optimization challenges for sub 90nm CMOS designs-What is the real cost of long battery life?
Silicon yield once was dominated by contaminants and particulates, making yield a process issue. But with today's electronics supply chain, multiple suspects may be indicted on manufacturability issues. Who is responsible for preventative actions in manufacturability and yield? The AUTHORs, representing a foundry, a fabless company, an IP provider, two EDA… (More)
Every year, the design and EDA communities are besieged by dire warnings about the impending doom of "design as we know it." Every year, another unpleasant physical effect from the evil depths of deep submicron physics surfaces, compromising our designs in new and vile ways. Every year, the same story: more nanometer woes. Rather than endorse a new winner… (More)