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As a result of advances in high-speed digital communications, researchers have begun to use collections of different high-performance machines in concert to execute computationally intensive application tasks. Existing high-performance machines typically achieve only a fraction of their peak performance on certain portions of such application programs ;(More)
—In a heterogeneous computing (HC) environment consisting of different types of machines, an application program is decomposed into subtasks, each of which is computationally homogeneous. The goal is to execute subtasks on the machines in such a way that the total program execution time is minimized. A mathematical framework is presented that models the(More)
The problem of statically estimating the execution time distribution for a task graph consisting of a collection of subtasks to be executed in a heterogeneous computing (HC) system is considered. Execution time distributions for the individual subtasks are assumed to be known. A mathematical model for the communication network that interconnects the(More)
The focus of this paper is the implementation and utilization of an inexpensive heterogeneous multicomputer cluster for the study of load balancing techniques. The basic conclusion of the paper is that excellent performance is possible provided that the proper choices among various parameters and implementation options of the load balancing schemes are(More)
An important problem in heterogeneous computing (HC) is predicting task execution time. A methodology is introduced for determining the execution time distribution for a given data parallel program that is to be executed in an SIMD, MIMD (SPMD), and/or mixed-mode SIMD/MIMD (SPMD) HC environment. The program is assumed to contain operations and constructs(More)
The work described here introduces a practical and accurate tool for predicting power consumption for FPGA circuits. The utility of the tool is that it enables FPGA circuit designers to evaluate the power consumption of their designs without resorting to the laborious and expensive empirical approach of instrumenting an FPGA board/chip and taking actual(More)