John H. Edmondson

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A new CMOS microprocessor, the Alpha 21164, reaches 1,200 mips/600 MFLOPS (peak performance). This new implementation of the Alpha architecture achieves SPECint92/SPECfp92 performance of 345/505 (estimated). At these performance levels, the Alpha 21164 has delivered the highest performance of any commercially available microprocessor in the world as of(More)
n September 1994, Digital Equipment Corporation introduced the 21164 Alpha microprocessor. This processor exceedU ed the performance level o f existing Alpha microprocessors by over 50 percent and delivered exceptional Performance on computing-intensive applications such as large database manipulation, scientific and technical simulation, CAD, and powerful(More)
A 300-MHz, custom 64-bit VLSI, second-generation Alpha CPU chip has been developed. The chip was designed in a 0.5-um CMOS technology using four levels of metal. The die size is 16.5 mm by 18.1 mm, contains 9.3 million transistors, operates at 3.3 V, and supports 3.3-V/5.0-V interfaces. Power dissipation is 50 W. It contains an 8-KB instruction cache; an(More)
The NVAX and NVAX+ CPU chips are high-performance VAX microprocessors that use techniques traditionally associated with RISC microprocessor designs to dramatically improve VAX performance. The two chips provide an upgrade path for existing VAX systems and a migration path from VAX systems to the new Alpha AXP systems. The design evolved throughout the(More)
0740-7475/97/$10.00 © 1997 IEEE 25 THE COMPLEXITY OF THE CIRCUITS and functions packed on the Alpha 21164 microprocessor, aggressive performance targets, tight design resources, and rapid development schedule raised many testability issues. At the same time, these factors also made insertion of testability solutions on the chip challenging, if not(More)
High-speed I/O circuits, once used only for PHYs, are now widely used for intra-system signaling as well because of their bandwidth, power, area, and cost advantages. This technology enables chips with over 1 Tb/s of I/O bandwidth today and over 10 Tb/s of bandwidth by 2010 as both signaling rates and number of high-speed I/Os increase with process scaling.(More)
Clock recovery circuits are among the most critical components in communication systems. A dual-loop architecture, in which the frequency synthesizer and the clock aligner are separated, has been used extensively due to the conflicting needs to suppress jitter accumulation and filter noisy input [1]. Among different frequency synthesis architectures, a(More)