John G. McRory

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—A 40-dB dynamic range, dc–4-GHz parallel-summa-tion logarithmic amplifier is presented in this paper. The amplifier realizes a piecewise approximation to an exact logarithmic response. A design procedure that yields breakpoints on the exact response is described, along with delay-matching networks for parallel-summation logarithmic amplifiers. The(More)
most cases, these works may not be reposted without the explicit permission of the copyright holder. Abstract— A true logarithmic response amplifier based on a parallel signal path topology is described in this paper. The parallel topology provides wide band-width response compared to conventional series cascaded topologies. The amplifier has been(More)