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In order to adequately account for nanometer effects during timing analysis, archaic standard cell models must be replaced. Simplifying assumptions used during characterization, such as nearly linear voltage inputs or lumped-capacitance loads, are no longer valid. Signal integrity analysis further complicates the characterization process because the typical(More)
Cell characterization data is used by synthesis and timing verificationtools to compile and validate a cell netlist which meets timingconstraints imposed by the designer. Characterization tablescontain data for multiple, simple equations representing a cell's behaviorand are an alternative to the single, monolithic characteristicequation. Data in the table(More)
SPICE based circuit simulation is a traditional workhorse in the VLSI design process. Given the pivotal role of SPICE in the IC design flow, there has been significant interest in accelerating SPICE. Since a large fraction (on average 75%) of the SPICE runtime is spent in evaluating transistor model equations, a significant speedup can be availed if these(More)
The design of complex mixed-signal system-on-a-chip (SOC) designer poses challenging requirements on the simulation design environment. The simulation platform has to include simulations at the behavioral, gate and transistor-level which have traditionally been done in separate environments. As the scaling trend continues, the designer needs additional(More)
  • Francis Croix, Martin Wong, +12 authors Tamara Cryar
  • 2002
Dedicated to those people in my life whose sacrifice and support made this possible. Acknowledgments This dissertation would not be possible were it not for the support and encouragement of my research advisor, Professor Martin Wong. Even during those inevitable lulls in which progress was measured in weeks or months, Professor Wong's unwavering confidence(More)
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