John Chappel

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A novel VLSI implementation of the Viterbi algorithm based on a cascade architecture is presented. Survivor sequence memory management is implemented using a new single read pointer traceback technique. The overall design for a 16-qtate, rate 1/2 decoder requires about 26000 transistors and a core area of 8.5 mma in a 1.2 pm two-level metal CMOS technology.(More)
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