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between the execution pipe and a larger main cache [1,2,6]. These techniques, however, often degrade the overall system performance. In this paper, we propose using a small instruction buffer, also called a loop cache, to save power. A loop cache has no address tag store. It consists of a direct-mapped data array and a loop cache controller. The loop cache(More)
<italic>Many portable and embedded applications are characterized by spending a large fraction of execution time on small program loops. To improve performance, many embeded systems use special instructions to handle program loop executions. These special instructions, however, consume opcode space, which is valuable in the embedded computing environments.(More)
The M • CORE microRISC architecture has been developed to address the growing need for long battery life among today's portable applications. In this paper, we will present the low-power design techniques and architectural trade-offs made during the development of this processor. Specifically, we will discuss the initial benchmarking, the development of the(More)
Lactococcus lactis NZ9010 in which the las operon-encoded ldh gene was replaced with an erythromycin resistance gene cassette displayed a stable phenotype when grown under aerobic conditions, and its main end products of fermentation under these conditions were acetate and acetoin. However, under anaerobic conditions, the growth of these cells was strongly(More)
The M • CORE microRISC architecture has been developed to address the growing need for long battery life among today's portable applications. In this paper, we present the architectural enhancements of the M3 processor , the successor to the original M • CORE M2 architecture. Specifically, we discuss the instruction buffer and pipeline enhancements, the(More)
The M • CORE TM RISC architecture has been developed to address the growing need for long battery life among today's embedded applications [4]. In this paper, we present several architectural enhancements to the M • CORE M3 processor. Specifically, we discuss the burst mode memory enhancements, the instruction fetch enhancements, the selectable branch(More)
The M • CORE M3 microprocessor core is currently being developed at the Motorola M • CORE Technology Center. It is targeted for the high performance, low cost and low power embedded markets. In this paper, we will present assembly-level optimization techniques for the M3 processor core. In particular, we will describe how software can take advantage of the(More)
The M • CORE microRISC architecture has been developed to address the growing need for long battery life among today's portable applications. In this paper, we will present the low-power design techniques and architectural trade-offs made during the development of this processor. Specifically, we will discuss the initial benchmarking, the development of the(More)
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