Johann Knechtel

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3-D chips rely on massive interconnect structures, i.e., large groups of through-silicon vias coalesced with large multibit buses. We observe that wirelength optimization, a classical technique for floorplanning, is not effective while planning massive interconnects. This is due to the interconnects' strong impact on multiple design criteria like(More)
Among 350 children with myelomeningocele 18 with elevated leak point pressures were managed by urethral dilation and followed for 1 to 5 years. Longitudinal measurements of bladder compliances revealed durable improvement in the pressure-volume relationships after dilation. These data suggest that noncompliant bladders are acquired because of high outlet(More)
Three-dimensional ICs promise to significantly extend the scale of system integration and facilitate new-generation electronics. However, progress in commercial 3D ICs has been slow. In addition to technology-related difficulties, industry experts cite the lack of a commercial 3D EDA tool-chain and design standards, high risk associated with a new(More)
The current trend towards 3D integration requires new layout representations specifically designed to take 3D-specific constraints into account and to facilitate efficient design algorithms. We observe that it is difficult to compare and evaluate these layout-specific data structures. In this paper, we first present a detailed investigation of modern layout(More)
In 3D-IC integration and its implied resource optimization, a particularly critical resource is <i>deadspace</i> --- regions <i>between</i> floorplan blocks. Deadspace is required for through-silicon via (TSV) planning and other related design tasks, but the effective use of this limited and highly-contested resource requires effort. While most previous(More)
Three-dimensional integrated circuits rely on optimized interconnect structures for blocks which are spread among one or multiple dies. We demonstrate how 2D and 3D block alignment can be efficiently utilized for structural planning of different interconnects. To realize this, we extend the corner block list and provide effective techniques for 3D layout(More)
The concept of 3D chip stacks has been advocated by both industry and academia for many years, and hailed as one of the most promising approaches to meet ever-increasing demands for performance, functionality and power consumption going forward. However, a multitude of challenges has thus far obstructed large-scale transition from "classical" 2D chips to(More)
Three-dimensional integrated circuits hold great promise for performance improvement and power savings, by reducing space and wiring. However, the technology comes with new challenges already during early stages such as the development of adequate floorplan representations. Moreover, it is required to deal with increased thermal stress in 3D integrated(More)
Split manufacturing is a promising technique to defend against fab-based malicious activities such as IP piracy, overbuilding, and insertion of hardware Trojans. However, a network flow-based proximity attack, proposed by Wang et al. (DAC’16) [1], has demonstrated that most prior art on split manufacturing is highly vulnerable. Here in this work, we present(More)
The reuse of predesigned intellectual property (IP) blocks is critical for the commercial success of three-dimensional (3D) electronic circuits. In practice, IP blocks can be specified as rectangular as well as rectilinear 2D blocks. The 3D equivalent of 2D rectilinear blocks, orthogonal polyhedra, may be utilized for modeling tightly interconnected(More)