Joel M. Tendler

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The IBM POWER4 is a new microprocessor organized in a system structure that includes new technology to form systems. The name POWER4 as used in this context refers not only to a chip, but also to the structure used to interconnect chips to form systems. In this paper we describe the processor microarchitecture as well as the interconnection architecture(More)
microarchitecture B. Sinharoy R. N. Kalla J. M. Tendler R. J. Eickemeyer J. B. Joyner This paper describes the implementation of the IBM POWER5e chip, a two-way simultaneous multithreaded dual-core chip, and systems based on it. With a key goal of maintaining both binary and structural compatibility with POWER4e systems, the POWER5 microprocessor allows(More)
IBM introduced Power4-based systems in 2001. The Power4 design integrates two processor cores on a single chip, a shared second-level cache, a directory for an off-chip third-level cache, and the necessary circuitry to connect it to other Power4 chips to form a system. The dual-processor chip provides natural thread-level parallelism at the chip level.(More)
Clock-gating has been introduced as the primary means of dynamic power management in recent high-end commercial microprocessors. The temperature drop resulting from active power reduction can result in additional leakage power savings in future processors. In this paper we first examine the realistic benefits and limits of clock-gating in current generation(More)
of orders 3 through 7 is established Each method exhibits better stability properties than those of the backward dffferentmtlon formula of the same order. A new varmble-step-slze, variable-order integration algorithm incorporating these new cyclic methods is described This algorithm, realized as a Fortran program, is ideally suited for the numemcal(More)
IBM introduced Power4-based systems in 2001. The Power4 design integrates two processor cores on a single chip, a shared second-level cache, a directory for an off-chip third-level cache, and the necessary circuitry to connect it to other Power4 chips to form a system. The dual-processor chip provides natural thread-level parallelism at the chip level.(More)
and ZDENEK PICEL equations) DESCRIPTION T h e a l g o r i t h m given here is a c o m p l e m e n t to [1] where the t h e o r e t i c a l develop-m e n t a n d test results are described. A stiffly stable integration process using cyclic composite methods. ALGORITHM [ S u m m a r y i n f o r m a t i o n a n d p a r t of the listing is p r i n t e d here. T(More)
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