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In this paper we propose a QR-decomposition hardware implementation that processes complex calculations in the logarithmic number system. Thus, low complexity numeric format converters are installed, using nonuniform piecewise and multiplier-less function approximation. The proposed algorithm is simulated with several different configurations in a downlink(More)
As nowadays Direct Digital Frequency Synthesizers (DDFS) are used in a vast area of applications, the demand for simple and efficient hardware design and implementation methods is a highly important aspect. In this paper a new approach is introduced considering Automatic Nonuniform Piecewise linear function Approximation (ANPA). Automatic function(More)
The use of Orthogonal Frequency Division Multiplex (OFDM) modulation has become increasingly important for actual and future mobile communication systems [1]. Within this scope, Carrier Frequency Offset (CFO) compensation is indispensable [2]. Its underlying algorithm requires the calculation of trigonometric functions, which is difficult to achieve by(More)
The impact of power efficient wireless sensor networks (WSN) is getting more and more important, as it is built of battery driven sensor nodes (SN). Beside common low power techniques like voltage scaling, variable-rate sampling (VRS) has been exposed as an adequate possibility to minimize the transceiver activity [1]. In this paper a high performance(More)
In this paper the first low-latency architecture design and hardware implementation for structure-based inpainting to detect and complete isophotes in brain activity recording is presented. This novel mask-based compression and inpainting-based reconstruction methodology for correlated neural signals is especially important for the realization of(More)