Joao Carlos Bittencourt

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In this paper a compact and high throughput hardware structure is proposed allowing for the computation of the novel 128-bit CLEFIA encryption algorithm and its associated full key expansion. In the existing state of the art only the 128-bit key schedule is supported, given the needed modification to the CLEFIA Feistel network. This work shows that with a(More)
This paper presents two architectures for the Low Density Parity Check (LDPC) encoder, the first one based on a fully serial approach and the second one in a mixed way, as well as their respective realizations in ASIC. The proposed designs are capable of operating in 84 combinations of code rate and word size, according to the IEEE 802.22 Wireless Regional(More)
Searching for new process models which satisfy the embedded systems demands, has been reflected in efforts to develop reusable IP-cores based on the Rational Unified Process (RUP). Among the alternative process, highlight the ipPROCESS, a Brazilian initiative in order to create a standard and enhance the development of integrated circuit design in the(More)
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