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The decades-old synchronous memory bus interface has restricted many innovations in the memory system, which is facing various challenges (or walls) in the era of multi-core and big data. In this paper, we argue that a message based interface should be adopted to replace the traditional bus-based interface in the memory system. A novel message interface(More)
— With the development of the scaling technologies, it's more susceptible to the transient faults for the modern microprocessors, so the error-correcting codes are used to detect and correct the errors in caches. In this paper, an enhanced architecture is proposed for the selective use of strong multi-bit ECC, where the main character is the extended L2(More)
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