Jiunn-Yann Tsai

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The gate oxide thickness increase in PMOSFET devices with BF/sub 2/ implanted p/sup +/ polysilicon gate is observed even when rapid thermal annealing (RTA) is used as a dopant activation thermal process. The increase of oxide thickness is studied as a function of RTA temperature, RTA time, and initial oxide thickness in the 35 /spl Aring/ regime and is(More)
The drain-induced-barrier-lowering (DIBL) considerations of the extended drain structure were studied using two-dimensional (2-D) device simulations in the tenth-micrometer regime. We found that the drain extension length must be kept at a minimum in order to reduce the transistor cell area and to improve the device transconductance, G/sub m/. However,(More)
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