Jiri Jenícek

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This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores designed according to the IEEE 1500 standard. The system spares memory and keeps acceptable test access mechanism requirements. The diagnostic system uses a built-in processor for(More)
Application dependent FPGA testing can reduce time and memory requirements comparing with the tests that exercise complete FPGA structure. This paper describes a methodology of FPGA testing that does not require reconfiguration of the tested hardware and thus it preserves conditions that caused erroneous behavior of the FPGA during its function. We show(More)
We propose a sequential test pattern decompressor enabling dynamic reseeding. It reduces dependency between the decompressor output bits during the first few clock cycles after decompressor reset. Due to this fact, a lower number of clock cycles is necessary to be performed in order to encode test patterns. We evaluated features influencing the(More)