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In the new TSPC flipflops, speed and power bottlenecks of the original TSPC and the existing differential flipflops are removed. Delays are reduced by factors of 2.0, 2.2 and 2.4 for the dynamic, the semi-static and the fully-static flipflops, respectively. In the same time, power consumptions are also reduced so the power-delay products are reduced by(More)
The interconnects between chips are gaining in importance. We study a line-receiver to find out what is the limit of transmission speed onto a CMOS chip. The high tracking-speed of an NMOS sampling switch is used together with parallelism to attain high data-rates. 4 Gsamples/s sample-rate and 2 Gbit/s bit-rate (two samples per bit) has been shown(More)
  • Gang Xu, Jiren Yuan
  • IEEE Transactions on Circuits and Systems II…
  • 2005
This brief focuses on the performance analysis of general charge-sampling circuits for signal capture. The theoretical analysis in the brief can be applied not only for weak signal capture, but also for the normal signal sampling. Based on a general charge-sampling model, the transfer function, the noise performance, and the clock jitter tolerance are(More)
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