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Coarse-grained reconfigurable architectures aim to achieve both goals of high performance and flexibility. However, existing reconfigurable array architectures require many resources without considering the specific application domain. Functional resources that take long latency and/or large area can be pipelined and/or shared among the processing elements.(More)
Interconnect delay should be considered together with computation delay during architectural synthesis in order to achieve timing closure in deep submicrometer technology. In this paper, we propose an architectural synthesis technique for <i>distributed-register architecture,</i> which separates interconnect delay for data transfer from component delay for(More)
×ØÖÖÖØ In this paper, we propose a method for performance improvement of multi-processor systems cosimulation by reducing synchronization overhead between multiple simulators. To reduce the amount of simulator synchronization, we predict synchronization time points based on a static analysis of application software running on each processor. In the(More)
– Coarse-grained reconfigurable architectures have become more attractive with the increasing requirement of more flexibility and higher performance in embedded systems design. In this paper, we suggest a design space exploration flow that enables effective optimization of reconfigurable architectures through SystemC Modeling. In the suggested flow,(More)
This paper presents a case study on fast prototyping of a wireless CDMA cellular phone system. We set up a fast prototyping flow which aims at reducing the coverification time. We captured executable specifications of the system with Ptolemy and Polis tools. We developed a prototyping board, a board debugger which provides in-circuit emula-tion functions,(More)
To achieve fast verification of the software part of embedded system, we propose to run the target processor optimistically , which effectively reduces the synchronization overhead with other simulators. For the optimistic processor execution, we present a processor execution platform and state saving/restoration methods. We performed optimistic execution(More)
<italic>In estimating the performance of multiple-cache IP-based systems, we face a problem of interdependency between cache configuration and system behavior. In this paper, we investigate the effects of the interdependency on system performance in a case study. We present a method that gives fast and accurate estimation of system performance by simulating(More)
We demonstrate the appropriacy of using laser distance meter as the accurate, cost-effective, simple solution for position estimation within precise 3D point cloud map in urban environment scenario. Our approach treats trilateration method with minimum error selection algorithm for better position accuracy of landmark. We validate the performance of our(More)
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